Printed circuit board and method of manufacturing the same

ABSTRACT

A printed circuit board and a method of manufacturing the same are provided. The printed circuit board includes a core board having a cavity that penetrates through a region of a core layer, an electronic component embedded in the cavity, side surfaces of the cavity contacting the electronic component, and insulating layers disposed on opposite surfaces of the core board.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 USC 119(a) of Korean PatentApplication No. 10-2015-0033786 filed on Mar. 11, 2015, in the KoreanIntellectual Property Office, the entire disclosure of which isincorporated herein by reference for all purposes.

BACKGROUND

1. Field

The present disclosure relates to a printed circuit board and a methodof manufacturing the same.

2. Description of Related Art

In general, warpage may occur in a printed circuit board (PCB) due todifferences in the physical properties of materials stacked thereon suchas, for example, due to mismatches between coefficients of thermalexpansion (CTE). The warpage of the PCB as described above is asignificant factor having a large influence on the PCB and a packageprocess. Consequently, the degree of warpage has an important influenceon package yield. Further, in a case of a recent embedded PCB in whichan electronic component is embedded, a warpage may occur due todifferences in physical properties between the electronic component andthe PCB. Particularly, as a size of the electronic component to beembedded increases (or as a ratio of electronic component/printedcircuit board increases), warpage tends to increase.

An object of embedding electronic components is to implement a greaternumber of functions in the same area. As a size of an embedded componentis increased, that is, when the embedded component corresponds to ahigh-value integrated circuit (IC), an effect of the surroundingenvironment may be decreased and performance of an electronic componentmay be significantly increased by embedding the component. Therefore, itis important to secure a yield with respect to the embedded componentand multiple functions by additionally applying surface-mount technology(SMT).

At the time of embedding the electronic component, a warpage problemcaused by differences in mechanical properties between the component andan interior material should be technically solved for mass-production ofa component-embedded board. Particularly, in a case of an active elementof which an area ratio of an embedded component in a package is large, atechnology of decreasing warpage may play a critical role in adopting atechnology of embedding a component in the corresponding package.

Currently, in order to embed the electronic component, a method forsequentially stacking prepreg (PPG) on upper and lower portions ofcopper clad laminate (CCL) has been used. In this case, there aredifferences in degrees of curing, curing shrinkage, and the like,between the upper and lower PPG on the CCL, which may cause warpage.

SUMMARY

This Summary is provided to introduce a selection of concepts in asimplified form that are further described below in the DetailedDescription. This Summary is not intended to identify key features oressential features of the claimed subject matter, nor is it intended tobe used as an aid in determining the scope of the claimed subjectmatter.

In one general aspect, a printed circuit board including a core boardhaving a cavity that penetrates through a region of a core layer, anelectronic component embedded in the cavity, side surfaces of the cavitycontacting the electronic component, and insulating layers disposed onopposite surfaces of the core board.

The insulating layers on opposite surfaces of the core board may havedegrees of curing and curing shrinkages that are substantially equal toeach other.

The core board may further include inner layer circuit patternscontacting at least one of upper and lower surfaces of the core layer.

A lower surface of the electronic component may be positioned on thesame plane as lower surfaces of the inner layer circuit patterns formedon the lower surface of the core layer.

The core board may further include a first via formed in the core layerand electrically connecting the inner layer circuit patterns formed onthe upper and lower surfaces of the core layer to each other.

The general aspect of the printed circuit board may further includeouter layer circuit patterns formed on at least one surface of theinsulating layer, and second and third vias provided in the insulatinglayer and electrically connecting the outer layer circuit patterns tothe inner layer circuit patterns or the electronic component,respectively.

The general aspect of the printed circuit board may further include acontact pad interposed between the electronic component and the thirdvia in the insulating layer.

In another general aspect, a method of manufacturing a printed circuitboard involves forming a cavity to penetrate through a region of a corelayer of a core board such that the cavity has a size equal to orsmaller than a size of an electronic component to be embedded in thecavity, expanding the cavity by a first external stimulus to a sizelarger than a size of the electronic component, embedding the electroniccomponent in the expanded cavity, contracting the cavity in which theelectronic component is embedded by a second external stimulus such thatside surfaces of the cavity contact the electronic component, andforming insulating layers on opposite surfaces of the core boardembedded with the electronic component.

At least one of the first and second external stimuli may be atemperature.

The second external stimulus may have a temperature lower than atemperature of the first external stimulus.

The first external stimulus may be heating, and the second externalstimulus may be cooling.

At time of contracting the cavity of the core board embedded with theelectronic component, the electronic component may be inserted into thecavity.

Other features and aspects will be apparent from the following detaileddescription, the drawings, and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic plan view illustrating main features of an exampleof a printed circuit board according to the present disclosure.

FIG. 2 is a cross-sectional view taken along line I-I′ of the exampleillustrated in FIG. 1.

FIG. 3 is a flow chart illustrating an example of a method ofmanufacturing a printed circuit board according to the presentdisclosure.

FIGS. 4A through 8B are process views illustrating the example of themethod of manufacturing a printed circuit board of FIG. 3.

FIGS. 4A and 4B are a plan view and a cross-sectional view,respectively, illustrating an example of a core board in which a cavityin which an electronic component will be embedded is formed.

FIGS. 5A and 5B are a plan view and a cross-sectional view,respectively, illustrating the example of the core board in which thecavity formed therein is expanded.

FIGS. 6A and 6B are a plan view and a cross-sectional view,respectively, illustrating the example of the core board of which theelectronic component is embedded in the cavity.

FIGS. 7A and 7B are a plan view and a cross-sectional view,respectively, illustrating an example of an electronic component and thecavity of which side surfaces contact each other due to contraction ofthe cavity.

FIGS. 8A and 8B are a plan view and a cross-sectional view,respectively, illustrating insulating layers simultaneously formed onand below the example of the core board embedded with the electroniccomponent.

Throughout the drawings and the detailed description, the same referencenumerals refer to the same elements. The drawings may not be to scale,and the relative size, proportions, and depiction of elements in thedrawings may be exaggerated for clarity, illustration, and convenience.

DETAILED DESCRIPTION

The following detailed description is provided to assist the reader ingaining a comprehensive understanding of the methods, apparatuses,and/or systems described herein. However, various changes,modifications, and equivalents of the methods, apparatuses, and/orsystems described herein will be apparent to one of ordinary skill inthe art. The sequences of operations described herein are merelyexamples, and are not limited to those set forth herein, but may bechanged as will be apparent to one of ordinary skill in the art, withthe exception of operations necessarily occurring in a certain order.Also, descriptions of functions and constructions that are well known toone of ordinary skill in the art may be omitted for increased clarityand conciseness.

The features described herein may be embodied in different forms, andare not to be construed as being limited to the examples describedherein. Rather, the examples described herein have been provided so thatthis disclosure will be thorough and complete, and will convey the fullscope of the disclosure to one of ordinary skill in the art.

In the drawings, the shapes and dimensions of elements may beexaggerated for clarity, and the same reference numerals will be usedthroughout to designate the same or like elements.

According to one example, the present disclosure provides a printedcircuit board in which warpage of a board may be decreased.

According another example, the present disclosure also provides a methodof manufacturing a printed circuit board capable of decreasing warpageof a board.

According to yet another example, the present disclosure provides atechnique for decreasing warpage of a board due to a difference inmechanical property values, a difference in coefficients of thermalexpansion (CTE) between an electronic component and an interiormaterial, or differences in degrees of curing and curing shrinkagebetween upper and lower insulating layers sequentially stacked onopposite surfaces of a core board.

According to yet another example, a printed circuit board in which adiscontinuous CTE gap is not present between a cavity provided in a coreboard and an electronic component embedded in the cavity is provided.The printed circuit board may include upper and lower insulating layersformed on opposite surfaces of the core board and having degrees ofcuring and curing shrinkage equal or similar to each other.

According to yet another example, the present disclosure provides amethod of manufacturing a printed circuit board in which an electroniccomponent may be embedded without using a filler having a relativelylarge CTE between a cavity and the electronic component by expanding andcontracting a cavity, and simultaneously forming insulating layers onopposite surfaces of the core board. In this case, the cavity formed inthe core board may be expanded and contracted using an external stimulussuch as a temperature.

Hereinafter, a printed circuit board according to the present disclosureand a method of manufacturing the same will be described in detail withreference to FIGS. 1 through 8B.

In the present embodiment, horizontal and perpendicular directions ofthe printed circuit board are defined based on an upper surface of acore layer.

FIG. 1 is a schematic plan view illustrating main features of an exampleof a printed circuit board according to the present disclosure, and FIG.2 is a cross-sectional view of the example taken along line I-I′ of FIG.1.

As illustrated in FIGS. 1 and 2, the printed circuit board 100 s includea core board 110 in which a cavity 118 is provided in a core layer 112,an electronic component 120 embedded in the cavity 118, and insulatinglayers simultaneously formed on opposite surfaces of the core board 110embedded with the electronic component 120.

Further, the printed circuit board 100 includes inner layer circuitpatterns 114, outer layer circuit patterns 140, vias 116, 150, and 170,and a contact pad 160.

The core board 110 includes the core layer 112, the inner layer circuitpatterns 114 formed on opposite surfaces, for instance, upper and lowersurfaces of the core layer 112, a first via 116 electrically connectingthe inner layer circuit patterns 114 formed on upper and lower surfacesof the core layers 112 to each other, and the cavity 118 formed in thecore layer 112.

The core layer 112 may serve as a support member while providing a spacein which a semiconductor device, for instance, the electronic component120 is embedded. The core layer 112 may be formed of an insulatingmaterial such as prepreg (PPG), or the like, and the insulating materialmay be impregnated into a core formed of glass cloth or fabric cloth,such that rigidity capable of corresponding to warpage may be imparted.

The inner layer circuit patterns 114 formed on opposite surfaces of thecore layer 112 may be used as wiring layers of a multilayer printedcircuit board.

The inner layer circuit patterns 114 as described above may be formed ofa conductive material, for example, metal foil, a metal layer, or thelike. An example of the metal foil may include copper foil, aluminumfoil, nickel foil, chromium foil, gold foil, silver foil, and the like.An example of the metal layer may contain copper, aluminum, nickel,chromium, gold, silver, or alloys thereof.

In view of improvement of conductivity and thinness, the inner layercircuit patterns 114 may be formed of copper foil. For example, the coreboard 110 may be formed of a copper clad laminate (CCL).

The inner layer circuit patterns 114 formed on opposite surfaces of thecore layer 112 may be electrically connected to each other by the firstvia 116 penetrating perpendicularly through the core layer 112 based onthe upper surface of the core layer 112.

Meanwhile, although upper and lower inner layer circuit patterns 114formed on opposite surfaces of the core layer 112 and the first via 116connecting the upper and lower inner layer circuit patterns 114 to eachother are illustrated in FIG. 2, the inner layer circuit patterns 114and the first via 116 are not necessarily limited thereto. For instance,the inner layer circuit patterns 114 may be formed on either of theupper and lower surfaces of the core layer 112 or may be formed on asurface of another layer instead of the core layer 112, and thus, thefirst via 116 may also be omitted or a position of the first via 116 mayalso be changed. For instance, positions, the numbers, shapes, and thelike, of the inner layer circuit patterns 114 and the first via 116 maybe variously changed depending on a design of the board.

The cavity 118 provided in the core layer 112, which is a space forembedding the electronic component 120, may be formed to perpendicularlypenetrate through one region of the core layer 112 based on the uppersurface of the core layer 112 in order to miniaturize and thin theprinted circuit board.

The electronic component 120 may be embedded in the cavity 118 of thecore board 110 without the aid of a separately provided filler tothereby be fixed thereto. In this case, a side surface of the electroniccomponent 120 may contact a side surface of the cavity 118. An interfacebetween the side surfaces of the electronic component 120 and the cavity118 may become a contact surface.

As illustrated in FIG. 1, a gap layer for the filler does not existbetween the side surfaces of the electronic component 120 and the cavity118. The reason for this is that a size (area) of the electroniccomponent 120 and a size of the cavity 118 are substantially equal toeach other. As a result, the electronic component 120 may be in the samestate as a state in which the electronic component isinterference-fitted into the cavity, which is a state in which theelectronic component 120 is structurally engaged with the cavity 118.

In the case of an existing embedded printed circuit board, since acavity is relatively large, as compared to an electronic component to beembedded therein, an element such as bonding tape is required in orderto embed an electronic component in a core cavity, and the electroniccomponent is fixed into the cavity by inserting a filler such as aresin, or the like, into a margin portion of the cavity. In this case,since a discontinuous gap filled with a resin having a large coefficientof thermal expansion (CTE) is generated between the CCL having a smallCTE and the electronic component in the horizontal direction of theboard, warpage of the board may occur due to mismatch of the CTE betweenthe electronic component and an interior material. Further, in order tofill the margin portion of the cavity with the filler such as the resin,or the like, upper and lower insulating layers of a core board aresequentially stacked, such that warpage of the board may occur due to adifference in curing degree between the upper and lower insulatinglayers. Here, the sequential stacking may mean that the upper and lowerinsulating layers are not simultaneously stacked but are sequentiallystacked.

However, according to the present example, since an inflection point ofa mechanical properties value, for instance, the CTE does not existbetween the core board 110 and the electronic component 120 by removinga discontinuous CTE gap in the horizontal direction of the printedcircuit board 100 due to a structure in which the filler having a largeCTE such as the resin, or the like, does not exist between the cavity118 of the core board 110 and the electronic component 120 embeddedtherein, an amount of warpage occurrence of the board may be decreased.

Meanwhile, in a case in which the inner layer circuit pattern 114 isformed on the lower surface of the core layer 112, a lower surface ofthe electronic component 120 may be positioned on the same plane as alower surface of the inner layer circuit pattern 114 formed on the lowersurface of the core layer 112.

The insulating layers 130 may be simultaneously stacked and formed onopposite surfaces of the electronic component 120 and the core board 110due to disposition of the electronic component 120 as described above.Here, the simultaneous stacking may mean that the upper and lowerinsulating layers are stacked simultaneously.

The insulating layers 130 may be formed of the insulating material suchas prepreg (PPG), or the like, and the insulating material may beimpregnated into the core formed of glass cloth or fabric cloth, suchthat rigidity capable of corresponding to warpage may be imparted. Inthis case, as an example of the insulating material, there is a generalthermosetting polymer resin suitable for build-up.

The insulating layers 130 simultaneously stacked in the perpendiculardirection may have equal or similar degrees of curing and curingshrinkage characteristics to each other on and below the core board 110.Here, the curing shrinkage may mean a shrinkage degree of a crosssection during the curing. The term “similar degree” refers to asimilarity of approximately 90%. For example, the average shrinkage of afirst insulating layer during a temperature change may result in alength difference in one direction. If the length difference of a secondinsulating layer is within approximately 90%, or within ±10% of thelength difference of the first insulating layer, the shrinkage degree ofthe first and second insulating layers may be described as beingsimilar.

The occurrence amount of warpage of the printed circuit board 100 due toa difference in the curing degree and curing shrinkage in theperpendicular direction may be decreased due to the configuration asdescribed above.

According to the embodiment, the outer layer circuit patterns 140 areformed on the exposed insulating layers 130 while being positioned tohave the insulating layers 130 interposed therebetween. The outer layercircuit patterns 140 are provided on an upper surface of the upperinsulating layer 130 formed on an upper portion of the core layer 112,and the outer layer circuit patterns 140 are provided on a lower surfaceof the lower insulating layer 130 formed on a lower portion of the corelayer 112. A material of the outer layer circuit patterns 140 asdescribed above may be the same as that of the inner layer circuitpatterns 114.

A second via 150 are formed to perpendicularly penetrate through theinsulating layers 130 between the inner layer circuit patterns 114 andthe outer layer circuit patterns 140, such that the inner layer circuitpatterns 114 electrically connect to the outer layer circuit patterns140 through the second via 150.

Meanwhile, although outer layer circuit patterns 140 stacked on upperand lower portions of the core layer 112 with the insulating layer 130interposed therebetween, and the second vias 150 are illustrated in FIG.2, the outer layer circuit patterns 140 and the second vias 150 are notnecessarily limited thereto. For instance, the outer layer circuitpatterns 140 and the second vias 150 may be variously changed dependingon the design of the board. For example, the outer layer circuitpatterns 140 may be formed only on one surface of the insulating layer130, and thus, the second vias 140 may be partially omitted.

Further, referring to FIG. 2, the contact pad 160 is formed on theelectronic component 120 in order to improve connectivity with theelectronic component 120. A material of the contact pad 160 as describedabove may be the same as that of the inner layer circuit patterns 114.

A third via 170 is formed to penetrate perpendicularly through theinsulating layer 130 between the contact pad 160 and the outer layercircuit pattern 140. Therefore, the contact pad 160 and the outer layercircuit pattern 140 electrically connect to each other through the thirdvia 170, such that the electronic component 120 and the outer layercircuit pattern 140 electrically connect to each other.

Meanwhile, in another example, the contact pad 160 may be omitted insome cases. In this case, the third via 170 may contact the electroniccomponent 120 to electrically connect the electronic component 120 andthe outer layer circuit pattern 140 to each other.

In the example of the printed circuit board 100 described above, thereis no discontinuous CTE gap in the horizontal direction, and theinsulating layers 130 may be simultaneously formed in the perpendiculardirection, such that the amount of warpage occurrence due to thedifference in the CTE in the horizontal direction and the difference incuring degree and curing shrinkage in the perpendicular direction may bedecreased. Therefore, low-warpage may be entirely implemented, such thatreliability may be excellent.

The method of manufacturing the printed circuit board according to thepresent embodiment as described above will be described as follows.

An example of a method of manufacturing a printed circuit boardaccording to FIGS. 1 and 2 will be described with reference to FIG. 3.The same reference numerals will be used with respect to the samecomponents as those in the embodiment illustrated in FIG. 1, andoverlapping descriptions of the same components will be omitted suchthat only differences will be described.

FIG. 3 is a flow chart illustrating an example of a method ofmanufacturing a printed circuit board according to the presentdisclosure, and FIGS. 4A through 8B are process views furtherillustrating the example of the method of manufacturing a printedcircuit board according to FIG. 3.

Referring to FIGS. 3 through 4B, in the example of the method ofmanufacturing a printed circuit board, first, an original cavity 118 ahaving a size (area) equal to or smaller than that of an electroniccomponent to be embedded in a core layer 112 of a core board 110 isformed (S310).

In detail, after preparing a core board 110 such as a CCL, or the like,of which inner layer circuit patterns 114 are provided on oppositesurfaces of the core layer 112 and a first via 116 is provided in thecore layer 112, the original cavity 118 a for in which an electroniccomponent may be embedded is formed to penetrate through one region ofthe core layer 112.

The original cavity 118 a may be formed to have a size equal to orsmaller than that of the electronic component to be embedded. An examplein which the original cavity 118 a is formed to have a size smaller thanthat of the electronic component to be embedded is illustrated in FIGS.4A and 4B.

As an example, the original cavity 118 a may be formed by processing aregion of the core layer in which the electronic component will beembedded using a laser drill such as an yttrium aluminum garnet (YAG)laser drill, CO₂ laser drill, or the like, a mechanical drill, or thelike.

Next, referring to FIGS. 3, 5A, and 5B, the original cavity 118 a ofFIG. 4A is expanded by a first external stimulus so as to have a sizelarger than that of the electronic component to be embedded (S320).

In this example, the first external stimulus may be some physical and/orchemical stimulation applied from the outside to the core board 110. Thefirst external stimulus may be, for instance, a temperature-relatedstimulus.

For example, the first external stimulus may be heating, which is one ofmethods capable of raising (increasing) a temperature of the core board110.

As an example, in the expanding of the cavity (S320), the core board 110including the original cavity 118 a of FIG. 4A may be maintained to havea high temperature of at least 100° C., preferably, about 100 to 300° C.for a predetermined time by heating.

In this case, when the temperature of the core board 110 is less than100° C., an expansion rate of the core layer 112 may be excessivelysmall, such that the cavity may not be sufficiently expanded to have adesired size. On the contrary, when the temperature thereof is more than300° C., the temperature may be higher than a melting point of the corelayer 112, such that it may be difficult to maintain a shape of the coreboard 110.

Therefore, the original cavity 118 a of FIG. 4A may be expanded under ahigh temperature environment, such that an expanded cavity 118 b havinga size larger than that of the electronic component to be embedded maybe formed.

A margin space for easiness of subsequent embedding of the electroniccomponent may be secured by forming the expanded cavity 118 b asdescribed above.

However, the expanding of the cavity is not limited thereto, but atemperature, a time, and the like, may be appropriately controlled inconsideration of the coefficient of thermal expansion (CTE) of thematerial of the core layer 112 constituting the core board 110.

Next, as illustrated in FIGS. 3, 6A, and 6B, the electronic component120 may be embedded in the expanded cavity 118 b (S330).

The embedding of the electronic component 120 (S330) may be performed bypositioning the electronic component 120 on the expanded cavity 118 b ofthe core board 110 after positioning the core board 110 on a substrate(not illustrated).

Therefore, in a case in which an inner layer circuit pattern 114 isformed on a lower surface of the core layer 112, a lower surface of theelectronic component 120 may be positioned on the same plane as a lowersurface of the inner layer circuit pattern 114 formed on the lowersurface of the core layer 112.

Then, referring to FIGS. 3, 7A, and 7B, the expanded cavity 118 b ofFIG. 6A is contracted by a second external stimulus so as to have a sizeequal to that of the embedded electronic component 120 (S340).

For example, the second external stimulus may be some physical and/orchemical stimulation applied from the outside to the core board 110embedded with the electronic component 120. For example, the secondexternal stimulus may be a temperature.

In detail, the second external stimulus may be cooling, which is one ofmethods capable of lowering a temperature of the core board 110.

The second external stimulus may be a temperature lower than the firstexternal stimulus required for expansion of the cavity, and thistemperature may be lower than the first external stimulus by at least80° C.

As an example, the contracting of the cavity (S340) may be performed bymaintaining the temperature of the core board 110 including the expandedcavity 118 b of FIG. 6A at room temperature, a temperature of about 20to 25° C., for a predetermined time.

In a case in which a temperature range of the second externalstimulation is outside of the above-mentioned range, contract of thecavity to the same size as that of the electronic component 120 may notbe sufficiently performed.

However, the contracting of the cavity is not limited thereto, andtemperature, time, or the like, at the time of cooling may beappropriately controlled in consideration of the coefficient of thermalexpansion (CTE) of the material of the core layer 112 constituting thecore board 110.

Therefore, the expanded cavity 118 b of FIG. 6A may be contracted by acooling treatment, such that a final cavity 118 having the same size asthat of the embedded electronic component 120 may be obtained.

In this case, side surfaces of the electronic component 120 and thecavity 118 may contact each other to thereby be fitted to each otherwithout an aid of a separately prepared filler, such that an interfacebetween the side surfaces of the electronic component 120 and the cavity118 may be formed as a contact surface.

As a result, since an existing resin filler having a large CTE is notincluded between the side surfaces of the electronic component 120 andthe cavity 118, a discontinuous CTE gap in the horizontal direction ofthe printed circuit board 100 may be removed, such that an occurrenceamount of warpage due to a difference in CTE in the horizontal directionmay be decreased.

Meanwhile, in order to allow the cavity to be expanded and contracted bythe external stimuli such as temperature, thermal expansioncharacteristics of the core layer 112 depending on temperature may beused by continuously performing the expanding of the cavity (S320), theembedding of the electronic component (S330), and the contracting of thecavity (S340).

Thereafter, as illustrated in FIGS. 3, 8A and 8B, insulating layers 130may be simultaneously stacked on opposite surfaces of the core board 110embedded with the electronic component 120 (S350), thereby completingthe printed circuit board 100.

The insulating layers 130 may be simultaneously stacked by preparing twosheets of prepreg (PPG) in which an outer layer circuit pattern 140,vias 150 and 170, a contact pad 160, and the like, are provided,positioning one sheet of prepreg (PPG) on each of the upper and lowersurfaces of the core board 110 embedded with the electronic component120, and performing the pressing and heating thereon.

In a case in which a cavity is larger than an electronic component,since there is a need to fill a gap generated in the cavity afterembedding the electronic component, generally, upper and lowerinsulating layers are formed on a core layer by a sequential stackingmethod. Since amounts of a resin used in the upper and lower insulatinglayers, thicknesses of the upper and lower insulating layers, or thelike, are different from each other due to the gap generated in thecavity, it is difficult to adjust degrees of curing, curing shrinkage,and the like, of the upper and lower insulating layers to the samelevel, such that the sequential stacking method as described above maybecome a cause of warpage.

In a case of using a simultaneous stacking method according to thepresent embodiment, an insulating material may be stacked so as to havea small thickness deviation between the upper and lower insulatinglayers, such that degrees of curing and curing shrinkages of the upperand lower insulating layers 130 may be almost the same as each other.Therefore, the occurrence amount of warpage due to the differences indegrees of curing and curing shrinkage in the perpendicular direction ofthe board may be decreased.

Further, in this example, at the time of stacking the insulating layers130, there is no need to fill a gap of the cavity 118, and adjustment ofan amount of a resin for filling the gap of the cavity may be omitted.Thus, an excessive decrease of a height of one side of the upper andlower insulating layers during the stacking, or the like, may beprevented, such that process reliability may be improved.

Meanwhile, since the outer layer circuit patterns 140, the vias 150 and170, the contact pad 160, and the like, may be formed in the insulatinglayers 130 by a method generally known in the art, a detaileddescription thereof will be omitted.

As described above, according to the present example, the printedcircuit board capable of decreasing warpage due to a structure in whichthe insulating layers are simultaneously formed on opposite surfaces ofthe core board in addition to a structure in which the Discontinuous CTEgap does not exist in the horizontal direction of the board may bemanufactured by newly introducing the expanding of the cavity and thecontracting of the cavity.

As set forth above, according to embodiments in the present disclosure,in the printed circuit board, since the side surfaces of the electroniccomponent and the cavity may contact each other, the Discontinuous CTEgap does not exist in the horizontal direction, and the insulatinglayers are simultaneously formed in the perpendicular direction, suchthat the occurrence amount of warpage due to the difference in the CTEin the horizontal direction and the difference in curing degree andcuring shrinkage in the perpendicular direction may be decreased.

Further, the printed circuit board capable of decreasing warpage due tothe structure in which there is no filler between the cavity andelectronic component and the structure in which the insulating layersmay be simultaneously formed may be manufactured by newly introducingthe expanding of the cavity and the contracting of the cavity.

While this disclosure includes specific examples, it will be apparent toone of ordinary skill in the art that various changes in form anddetails may be made in these examples without departing from the spiritand scope of the claims and their equivalents. The examples describedherein are to be considered in a descriptive sense only, and not forpurposes of limitation. Descriptions of features or aspects in eachexample are to be considered as being applicable to similar features oraspects in other examples. Suitable results may be achieved if thedescribed techniques are performed in a different order, and/or ifcomponents in a described system, architecture, device, or circuit arecombined in a different manner, and/or replaced or supplemented by othercomponents or their equivalents. Therefore, the scope of the disclosureis defined not by the detailed description, but by the claims and theirequivalents, and all variations within the scope of the claims and theirequivalents are to be construed as being included in the disclosure.

What is claimed is:
 1. A printed circuit board comprising: a core boardhaving a cavity that penetrates through a region of a core layer; anelectronic component embedded in the cavity, side surfaces of the cavitycontacting the electronic component; and insulating layers disposed onopposite surfaces of the core board.
 2. The printed circuit board ofclaim 1, wherein the insulating layers on opposite surfaces of the coreboard has degrees of curing and curing shrinkages that are substantiallyequal to each other.
 3. The printed circuit board of claim 1, whereinthe core board further comprises inner layer circuit patterns contactingat least one of upper and lower surfaces of the core layer.
 4. Theprinted circuit board of claim 3, wherein a lower surface of theelectronic component is positioned on the same plane as lower surfacesof the inner layer circuit patterns formed on the lower surface of thecore layer.
 5. The printed circuit board of claim 3, wherein the coreboard further comprises a first via formed in the core layer andelectrically connecting the inner layer circuit patterns formed on theupper and lower surfaces of the core layer to each other.
 6. The printedcircuit board of claim 3, further comprising: outer layer circuitpatterns formed on at least one surface of the insulating layer; andsecond and third vias provided in the insulating layer and electricallyconnecting the outer layer circuit patterns to the inner layer circuitpatterns or the electronic component, respectively.
 7. The printedcircuit board of claim 3, further comprising a contact pad interposedbetween the electronic component and the third via in the insulatinglayer.
 8. A method of manufacturing a printed circuit board, comprising:forming a cavity to penetrate through a region of a core layer of a coreboard such that the cavity has a size equal to or smaller than a size ofan electronic component to be embedded in the cavity; expanding thecavity by a first external stimulus to a size larger than a size of theelectronic component; embedding the electronic component in the expandedcavity; contracting the cavity in which the electronic component isembedded by a second external stimulus such that side surfaces of thecavity contact the electronic component; and forming insulating layerson opposite surfaces of the core board embedded with the electroniccomponent.
 9. The method of claim 8, wherein at least one of the firstand second external stimuli is a temperature.
 10. The method of claim 9,wherein the second external stimulus has a temperature lower than atemperature of the first external stimulus.
 11. The method of claim 10,wherein the first external stimulus is heating, and the second externalstimulus is cooling.
 12. The method of claim 8, wherein at the time ofcontracting the cavity of the core board embedded with the electroniccomponent, the electronic component is inserted into the cavity.